A Gate Level Simulator for Power Consumption Analysis

Power consumption of digital circuits has become a critical design parameter. As such, it is necessary that the system designer is able to estimate power consumption and correlate the results back to high level specifications. A gate level tool that estimates power consumption and correlates the results with functiona! modules and control states has been designed. This tool has produced estimations of the power consumption of twelve different implementations of the discrete cosine transform (DCT). These results are being used to judge the relative impact of high-leve! transformations, such as pipelinin$ and varying the amount of resource sharing and parallelism, on power dissipation for the D CT algorithm.